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Avatar
Apeshaft
Posts: 51
Supporter
Dear friends,

I here give you the first 3D rendering of the PCB.
What remains is finding the exact location for the
mounting holes.

2019-02-20 17:45
Avatar
StephanHo
From: EDDG, Germany
Posts: 1867
Supporter
Hi Oskar,

may it be that the two GND-connector-line from C1 and C2 ar connected to the CS connector of H1?

Is the PCB laminated on both sides?
Grüße,
Stephan (Time: UTC+2)
2019-02-20 23:46
Avatar
Apeshaft
Posts: 51
Supporter
Hi Stephan,

It sure does look like that is the case.
It is a two-layer PCB. Perhaps C1 and C2 are connected to GND via this line and that it then continues in the second layer. Is CS now connected to this line? I have used the auto router feature.
2019-02-21 01:19
Avatar
StephanHo
From: EDDG, Germany
Posts: 1867
Supporter
Please follow the lines with your eyes. If you get another result I'll buy me glasses ;)
Better is to look on your real PCB...
Grüße,
Stephan (Time: UTC+2)
2019-02-21 01:44
Avatar
Apeshaft
Posts: 51
Supporter
So obviously the auto router feature cannot be trusted? Perhaps I need to mark VCC and GND in the schematic so the router knows they can't be interconnected with anything else. I will add a better picture tomorrow, the schematic looks alright other than that the VCC and GND is not pointed out.
2019-02-21 01:59
Avatar
Apeshaft
Posts: 51
Supporter
So I think I got it sorted out. Also found and solved another problem with VCC being directly connected to the one
of the segment lines, glad I found that issue before manufacturing :rolleyes:

Bottom layer:



Top layer:

2019-02-21 14:15
Avatar
StephanHo
From: EDDG, Germany
Posts: 1867
Supporter
Hi Oskar,

please have a look on the top layer.

A lot of the lines are to close to each other, there are problems with etching.
Is it possible to tell your router to use smaller lines? You need the space between the lines because there is no static voltage but also frequencies.

If the tracks are too close to each other, you may have a resonant circuit that bothers you.
Normally, the gaps should be half the width of the track itself. 1mm track, 0,5mm gap.

I would have led the tracks of the individual segments together from the chip to the middle of the 1st display, down to the 2nd display, ran from below and then led to the 3rd display below the displays. In the upper displays as well. The other tracks then emerge almost by itself. An autorouter always routes in such a way that all tracks are optimal for it. Visually, that's not always good. That with the gaps should not have been so from an autorouter.

EDIT: The capacitors are also not optimally placed. They should be as close as possible to the ICs, so that the oscillation behavior is optimally suppressed. Instead of 1μF I would have taken 100nF.
Grüße,
Stephan (Time: UTC+2)
2019-02-21 19:17
Avatar
Apeshaft
Posts: 51
Supporter
Thank you Stephan,

I see now that the lines have merged.
I know I can set thinner lines and also set the minimum gap so I will fix this. The lines are now 1 mm, perhaps 0.8 is sufficient.
When you say as close as possible to the ICs I take it that you mean as close as possible to VCC and GND inputs of the IC? Will sort this too.
2019-02-21 19:31
Avatar
StephanHo
From: EDDG, Germany
Posts: 1867
Supporter
You understand me the right way ;)
Grüße,
Stephan (Time: UTC+2)
2019-02-21 19:33
Avatar
Apeshaft
Posts: 51
Supporter
Allright, new version:

Bottom layer:



Top layer:

2019-02-21 19:49
Avatar
StephanHo
From: EDDG, Germany
Posts: 1867
Supporter
Hi Oskar,

the problem with the gaps seems solved. With the individual connections I noticed further no errors / problems
Grüße,
Stephan (Time: UTC+2)
2019-02-23 19:46
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